Methods and systems to improve uniformity in power fet arrays

ABSTRACT

A vertical, fin-based field effect transistor (FinFET) device includes an array of individual FinFET cells. The array includes a plurality of rows and columns of separated fins. Each of the separated fins is in electrical communication with a source contact. The vertical FinFET device also includes one or more rows of first inactive fins disposed on a first set of sides of the array of individual FinFET cells, one or more columns of second inactive fins disposed on a second set of sides of the array of individual FinFET cells, and a gate region surrounding the individual FinFET cells of the array of individual FinFET cells, the first inactive fins, and the second inactive fins.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims priority to U.S. Provisional Patent ApplicationNo. 63/172,545, filed on Apr. 8, 2021, the disclosure of which is herebyincorporated by reference in its entirety for all purposes.

BACKGROUND OF THE INVENTION

Vertical power transistors, in which the current flows from the topsurface of the transistor to the back or bottom surface of thetransistor substrate, are commonly used for controlling high currentsand high voltages, since they can be formed with a reduced area comparedto devices in which current flow through the transistor is lateral.

III-nitride materials, and in particular, gallium nitride (GaN), allowvertical FET-based power transistors to be fabricated with highbreakdown voltages (e.g., in excess of 1200 V) while offeringsignificant reductions in the specific on-resistance (i.e., theon-resistance of the device multiplied by the device area) compared tosilicon or silicon carbide materials.

Despite the progress made in the area of vertical power transistors,there is a need in the art for improved methods and systems related tovertical power transistors.

SUMMARY OF THE INVENTION

The present invention generally relates to the field of electronics, andmore specifically to semiconductor manufacturing technology. In aparticular embodiment, structures and methods of forming uniform arraysof vertical conducting FETs in a gate-all-around architecture areprovided. Embodiments of the present invention are applicable to avariety of different, vertical FET structures and gate configurations.

According to an embodiment of the present invention, a vertical,fin-based field effect transistor (FinFET) device is provided. Thevertical FinFET device includes an array of individual FinFET cells. Thearray includes a plurality of rows and columns of separated fins. Eachof the separated fins is in electrical communication with a sourcecontact. The vertical FinFET device also includes one or more rows offirst inactive fins disposed on a first set of sides of the array ofindividual FinFET cells, one or more columns of second inactive finsdisposed on a second set of sides of the array of individual FinFETcells, and a gate region surrounding the individual FinFET cells of thearray of individual FinFET cells, the first inactive fins, and thesecond inactive fins.

According to another embodiment of the present invention, a method offabricating a vertical, fin-based field effect transistor (FinFET)device is provided. The method includes providing a III-nitridesubstrate including a plurality of epitaxial layers, forming a metallayer coupled to one of the plurality of epitaxial layers, patterningthe metal layer to form source contacts, and forming a recess region inone or more of the plurality of epitaxial layers to define an active finarray, inactive fin columns, and one or more inactive fin rows. Each ofthe source contacts is in electrical communication with an active fin inthe active fin array. The method also includes regrowing a gate layer inthe recess region, forming a dielectric layer over the source contacts,and forming vias through the dielectric layer. The method furtherincludes forming a source pad metal over the dielectric layer and in thevias, wherein the source pad metal is in electrical communication withthe source contacts and forming a drain layer electrically coupled tothe III-nitride substrate.

Numerous benefits are achieved by way of the present disclosure overconventional techniques. For example, embodiments of the presentdisclosure provide methods and systems that provide uniform dimensionsin arrays of gate-all-around vertical field effect transistors. Theseand other embodiments of the disclosure, along with many of itsadvantages and features, are described in more detail in conjunctionwith the text below and corresponding figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified flowchart of a method of fabricating a verticalfin-based JFET using a regrown-gate approach according to an embodimentof the present invention.

FIGS. 2A through 2D are cross-sectional views showing intermediatestages of a method of fabricating a vertical fin-based JFET deviceaccording to an embodiment of the present invention.

FIG. 3 is a plan view of a fin pattern layout illustrating a fin array300 having a plurality of semiconductor fins having predetermined finheights according to an embodiment of the present disclosure.

FIGS. 4A and 4B show examples of a plan-view layout of an array of finswithout and with inactive fins, respectively, according to an embodimentof the present invention.

FIG. 5 shows a cross-section of an array of fins in an active fin arraycharacterized by regrowth non-uniformity according to an embodiment ofthe present invention.

FIG. 6 shows a cross-section of a fin in an active fin arraycharacterized by regrowth non-uniformity according to an embodiment ofthe present invention.

FIG. 7 shows a cross-section of an array of fins in an active fin arrayand inactive fin columns according to an embodiment of the presentinvention.

FIG. 8 shows a cross-section of a fin in an active fin array and aninactive fin row according to an embodiment of the present invention.

FIG. 9 shows a cross-section of an array of fins in an active fin arrayand inactive fin columns with a source pad metal according to anembodiment of the present invention.

FIG. 10 is a cross-section view of an alternative vertical, fin-basedgate-all-around JFET device using implanted or diffused gates accordingto an embodiment of the present invention.

FIG. 11 is a cross-section view of an alternative vertical, fin-basedgate-all-around MOSFET device according to an embodiment of the presentinvention.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

The present invention generally relates to the field of electronics, andmore specifically to semiconductor manufacturing technology. In aparticular embodiment, structures and methods of forming uniform arraysof vertical conducting FETs in a gate-all-around architecture areprovided. Embodiments of the present invention are applicable to avariety of different, vertical FET structures and gate configurations.

Power semiconductor devices including transistors and diodes are widelyused today in such applications as industrial power supplies, motordrives, consumer electronics, etc. A common application of powersemiconductor transistors is their use as switches in switch-mode powersupplies or motor drives. In such applications, the ability of thedevice to operate at high voltages (650V or 1200V, for example) and towithstand momentary overvoltage conditions (line surges or lightningstrikes on power lines, for example) are extremely important.

In addition, in order to reduce the resistance of the switch and reduceparasitic capacitances, etc., that limit switch speed, an increasedconductance per unit area is desirable. Switch transistors in which thecurrent flow is primarily vertical offer reduced resistance per area;this benefit can be further improved by arranging the control channel ofthe transistor to lie in the vertical direction, e.g., a “trench”channel transistor. The resistance of the transistor has severalcomponents, including the resistance of the transistor channel (theregion where current is directly controlled by the input gate voltage),the resistance of the “drift” region (the region designed to hold thebreakdown voltage of the transistor), and the resistance of the startingsubstrate, contacts, metals, etc.

Transistors with vertical current flow are typically designed with thedrain contact at the bottom surface of the chip, and the gate and sourcecontacts at the top surface of the chip.

In order to maximize the switch conductivity (minimize the switchresistance) and provide a uniform transient response for the device, thetransistor may be fabricated using an array of many smallvertical-channel switch devices surrounded by control gates (an array of“gate-all-around” transistors). The finished device has all sourcesconnected to a single electrode, the surrounding gates connected to acommon gate electrode, and a common drain electrode.

Improvements in switch resistance and capacitance can be made bychanging the semiconductor material from silicon to a wide bandgapmaterial such as gallium nitride, which offers a higher critical fieldfor breakdown; this allows the high-voltage drift region of the deviceto be made thinner and more heavily doped than with similar silicondevices, reducing the “specific resistance” (product of resistance andarea) of the drift region, and reducing the device on resistance for agiven die size.

Accordingly, for such wide bandgap transistors, the gate-all-aroundarray has a small area, and is typically fabricated with finelithographic features (e.g., minimum geometries of <0.5 μm),particularly for normally off JFETs where the built-in pn-junctiondepletion is used to turn off the device channel at zero bias. Thecontrol of these features is critical to the uniform operation of thedevice. For example, if the individual device in the gate-all-aroundarray is a vertical JFET or accumulation-mode MOSFET built on a vertical“fin”, variations in the width of the fin can cause significantvariation in the individual device leakage or threshold voltage. Suchvariations impact the overall leakage of the array or the on-resistanceof the array, and can affect the maximum voltage or switching efficiencyof the device.

Accordingly, embodiments of the present invention provide methods andsystems that provide uniform dimensions in arrays of gate-all-aroundvertical transistors.

A vertical FET transistor structure is described in U.S. Pat. No.9,117,839 (Kizilyalli, et al.) (the “839 structure”), the disclosure ofwhich is hereby incorporated by reference in its entirety for allpurposes. In the '839 structure, the transistor conducting channel isformed using a semiconductor “fin” created by patterning and etchingsurrounding material to a certain depth. A semiconductor material withan opposite doping type is epitaxially regrown (e.g., using metalorganicvapor phase epitaxy, or MOVPE) to be substantially planar to the top ofthe semiconductor “fin”. The regrown material serves as the gateelectrode of a vertical FET, and application of control voltages to thegate electrode modulates the conduction of current in the vertical “fin”channel between the top of the fin (“source”) and bottom of the fin(normally, the drift region which is further connected to the “drain”electrode via the semiconductor substrate).

In the '839 structure, the regrown gate material surrounds the fin. Anarray of fins can be fabricated with a common gate using this approach,with (for example) fins arranged in a number of rows and columns so thatthe total number of transistors achieves the desired on-resistancetarget for the final device.

Dimensional control of the fins is utilized to maintain uniform devicecharacteristics for each individual fin. Fin width control isparticularly useful to achieve a narrow threshold voltage and leakagecurrent distribution. Accordingly, embodiments of the present inventionprovide methods and systems to achieve the local uniformity of thelithography process that creates the masking layer that defines the fingeometry. The local uniformity of the etch processes that transfer themasking layer pattern into the hard mask and the GaN to create the finstructures is also provided by embodiments of the present invention.

The inventors have determined that the uniformity of both thelithography process and the etch processes can vary significantlybetween a region with a regular pattern and a region with a sparsepattern. Such a transition occurs at the edges of the array of fins. Forexample, the presence of a large sparse area next to a regular array canlead to differences in exposure dose due to proximity effects, whichwill cause the resist linewidth to vary between the center of the arrayand the edges of the array, with a resulting increase in the electricalvariation of the fin devices near the edge of the array. For example,the presence of a large sparse pattern area next to a regular patternarray can lead to differences in etch rate caused by variation in theamount of etchant consumed in the sparse pattern region vs. the amountconsumed in the regular pattern array. Such differences in etch rate canaffect both fin width and fin thickness, with a resulting increase inthe electrical variation of the fin devices near the edge of the array.

In addition, the inventors have determined that the uniformity of theregrown-gate process may be dependent on the local pattern density inthe array as discussed in U.S. patent application Ser. No. 17/135,436,the disclosure of which is hereby incorporated by reference in itsentirety for all purposes. The regrown-gate process in the '839 patentuses a selective area regrowth, where the tops of the fins are protectedby a growth mask. GaN does not grow on the mask, and thegallium-containing species that arrive on the mask diffuse to theexposed GaN surrounding the mask, thereby enhancing the epitaxial growthrate in the array relative to the growth rate on a uniform GaN surfacesuch as is found outside the array. Such variations in the growth ratecan lead to non-uniform thickness of growth on the fin sidewalls (whichwill affect the effective channel length of the switch, and can causevariation in leakage current at high voltage and in threshold voltage)for fins near the edges of the array. Variation in the growth rate mayalso affect the uniformity of dopant incorporation in the GaN duringregrowth, which in turn can cause variation in threshold voltage.

Similarly, the local incorporation rate of dopant species in the regrowngate (or through the use of a gas-phase doping technique, e.g., asdescribed in U.S. Provisional Patent Application No. 63/148,024, thedisclosure of which is hereby incorporated by reference in its entiretyfor all purposes), can be affected by the presence of a local mask orlocal topography. Doping of the regrown gate using a Mg-containingspecies (e.g., Cp2Mg) can vary near the edge of the array, causing localvariations in threshold voltage or leakage characteristics of thevertical devices in that region.

Therefore, embodiments of the present invention provide methods andstructures that can improve uniformity of lithography control, etchcontrol, and regrowth control (if used) to ensure uniform devicecharacteristics for the individual vertical fin-based transistors in thearray.

As described more fully herein, in some embodiments, an array of fins iscreated in a second epitaxial layer disposed on a first epitaxial layeron a substrate, to form a vertical power device, as described, forexample, in U.S. patent application Ser. No. 16/929,926 and U.S.Provisional Patent Application No. 63/051,979, the disclosures of whichare hereby incorporated by reference in their entirety for all purposes.The array is arranged in a regular pattern of rows and columns. For thediscussion below, the fins are assumed to be rectangular in plan view,with the long axis arranged in the direction of the column (they-direction) and the narrow axis arranged in the direction of the row(the x-direction). Various other arrangements of the fin array arepossible, for example, as discussed in U.S. patent application Ser. No.17/135,436, the disclosure of which is hereby incorporated by referencein its entirety for all purposes. In an embodiment, the conductivitytype of the first and second epitaxial layers and the substrate aren-type.

According to embodiments of the present invention, the array is designedto include extra fins, also referred to as inactive fins, at the ends ofeach row, and an at least one extra fin at the top and bottom of eachcolumn, thereby providing an excess number of fins compared to thenumber of fins utilized to achieve the desired on-resistance and currentcapacity for the transistor array. In some embodiments, the number ofextra fins at each end of a row is between one and ten. In anembodiment, the number of extra fins at each end of a row is five. In anembodiment, the extra fin at the top and bottom of each column isshorter in the y-direction than the other fins in the column.

The methods provided according to the present invention can also includeforming a gate region around the fins using one of several methods.Forming the gate region can include regrowing an epitaxial layer in theregion between the fins, as described in U.S. patent application Ser.No. 16/929,926 and U.S. Provisional Patent Application No. 63/051,979.In some embodiments, this epitaxial layer is p-GaN. Forming the gateregion can include implanting a gate region in the region between thefins (and optionally, in the sidewalls of the fins), where theconductivity type of the gate region is opposite that of the first andsecond epitaxial layers. In an embodiment, the gate region is p-type.These implantation methods are discussed in U.S. Provisional PatentApplication Nos. 63/040,853, 63/044,693, and 63/148,024, the disclosuresof which are hereby incorporated by reference in their entirety for allpurposes. Forming the gate region can further include diffusing a gateregion in the region between the fins (and optionally, in the sidewallsof the fins), where the conductivity type of the gate region is oppositethat of the first and second epitaxial layers. In an embodiment, thegate region is p-type. In an embodiment, the dopant is diffused from asolid source. In an embodiment, the dopant is diffused from a gas-phasesource. In an embodiment, the dopant is one of Mg, Zn or Be. Thesediffusion methods are discussed in U.S. Provisional Patent ApplicationNos. 63/040,853, 63/044,693, and 63/148,024, the disclosures of whichare hereby incorporated by reference in their entirety for all purposes.

The methods described herein can also include forming a dielectric layeron the surfaces of the trench, and forming a metal gate electrode on thedielectric layer. The work function of the metal is such that the metalgate electrode depletes the fin at zero bias as described in U.S. PatentApplication No. 63/044,693, the disclosure of which is herebyincorporated by reference in its entirety for all purposes. Afterforming the gate region, the methods can include forming a source metalcontact to the tops of the fins. In an embodiment, this source metalcontact is formed on all of the fins. In an embodiment, this sourcemetal contact is not formed on the “extra” fins. After forming the gateregion, the methods can include forming a junction terminated edge (JTE)region, for example, as described in U.S. Patent Provisional ApplicationNos. 63/049,562 and 63/142,909, the disclosures of which are herebyincorporated by reference in their entirety for all purposes. Afterforming the JTE region, the methods can include forming a gate metalcontact to the gate region and after forming the gate metal contact,depositing an interlayer dielectric. The interlayer dielectric can bepatterned and etched to form through-holes to the source metal contact.In an embodiment, the through-holes are not formed on the “extra” fins.The methods can also include forming through-holes to the gate metalcontact in a region away from the array of fins. The methods can includedepositing a pad metal layer that extends through the through holes, andpatterning the pad metal layer so that one region (the source pad)connects all of the source metal contacts, and one region (the gate pad)connects to the gate metal contact.

Utilizing embodiments of the present invention, a structure is createdin which the array of active device fins is separated from the sparselypatterned region outside the array by a buffer region of extra fins. Theextra fins are not connected to the source electrode, and so do notcontribute to the current-carrying capability of the transistor array.The buffer region is sized such that the non-uniformities due to theproximity of the sparsely patterned region are reduced or minimized inthe array of active devices.

In an alternative embodiment, a mask pattern can be created for an arrayof fins. The size of the mask pattern can be locally biased, using aspatially dependent algorithm, to adjust the size of the fins near theedge of the array to compensate for variations in lithography, etchingand epitaxial regrowth caused by the transition from the array to theregion outside the array. Patterning of the fins using the biased maskpattern can create the vertical transistors as described herein.

Embodiments of the present invention are applicable to arrays offin-based vertical FETs in which the current runs vertically along thefin and the arrays of fins are enclosed by a gate-all-around structureso that all fins have a common gate. The gate-channel interface can belocated on the vertical sidewall of the vertical fin. The FETs may beJFETs with regrown gates, implanted gates, or diffused gates, or theymay be MOSFETs, including accumulation-mode MOSFETs. The fin-basedvertical FETs can be fabricated using III-nitride semiconductors. In anembodiment, the fin-based vertical FETs are fabricated using GaN. In anembodiment, the number of inactive fin columns is between 1 and 10, andthe number of inactive fin rows is between 1 and 5. In an embodiment,the inactive fin rows use fins of shorter height (as discussed inrelation to FIG. 4B) than the active rows of the active array. In anembodiment, the inactive fin row height is comparable to the width ofthe region encompassed by the inactive fin columns.

FIG. 1 is a simplified flowchart of a method of fabricating a verticalfin-based JFET using a regrown-gate approach according to an embodimentof the present invention. Further details related to the fabricationprocess are provided in U.S. Patent Application Publication Nos.2021/0028312, and 2022/0020743, the disclosures of which are herebyincorporated by reference in their entirety for all purposes. Referringto FIG. 1, the method 100 of fabricating a vertical fin-based JFET usinga regrown-gate approach includes providing a III-nitride substrateincluding a plurality of epitaxial layers (110). In an embodiment, theIII-nitride substrate is an n-type GaN substrate having a resistivity ina range of about 0.020 ohm-cm. In one embodiment, the resistivity of then-type GaN substrate may be from about 0.001 ohm-cm to 0.018 ohm-cm,preferably less than 0.016 ohm-cm, and more preferably, less than 0.012ohm-cm. The plurality of epitaxial layers can include a firstIII-nitride epitaxial layer, a second III-nitride epitaxial layer formedon the first III-nitride epitaxial layer, and a third III-nitrideepitaxial layer formed on the second III-nitride epitaxial layer.

In some embodiments, the first III-nitride epitaxial layer is an n-typeGaN epitaxial layer that is ˜12 μm thick that is deposited on theIII-nitride substrate. The first III-nitride epitaxial layer can beepitaxially grown on the III-nitride substrate at a temperature between950 and 1100° C. and can be characterized by a first dopantconcentration, e.g., n-type doping with a dopant concentration of about1×10¹⁶ atoms/cm³. In some embodiments, the first III-nitride epitaxiallayer serves as a drift layer for the fin-based JFET and includes auniformly doped region (layer) on the III-nitride substrate and a gradeddoping region (layer) on the uniformly doped region. In an embodiment,the uniformly doped region has a thickness of about 12 μm, and thegraded doping region has a thickness of about 0.3 micron. In anembodiment, the surface of substrate is miscut from the c-plane at anangle to facilitate high-quality epitaxial growth for high-voltageoperation of the drift layer.

The second III-nitride epitaxial layer can be a III-nitride epitaxiallayer with a thickness of about 0.7 μm and can be characterized by asecond dopant concentration, e.g., n-type doping. The second dopantconcentration is higher than the first dopant concentration in someembodiments. In an embodiment, the second dopant concentration is about1.3×10¹⁷ atoms/cm³. The third III-nitride epitaxial layer can be aheavily doped III-nitride layer suitable for use in forming the sourceof the fin-based JFET.

Method 100 further includes forming a metal layer coupled to one of theplurality of epitaxial layers (112), forming a hard mask material on thethird III-nitride epitaxial layer, patterning the hard mask material toform a patterned hard mask, and patterning the metal layer to formsource contacts (114). The hard mask material may include multiplelayers. Method 100 further includes forming a recess region in thesecond III-nitride epitaxial layer using the patterned metal layer, forexample, by an etch process, e.g., a reactive ion etching (ME) process(116). The remaining portion of the second III-nitride epitaxial layerand the third III-nitride epitaxial layer between the recess regiondefines the active fins in the active fin array of the fin-based JFETdevice and the inactive fins in the inactive fin columns and the one ormore inactive fin rows. The method 100 further includes regrowing aIII-nitride epitaxial layer (e.g., a fourth III-nitride epitaxial layer)in the recess region (118). The regrown III-nitride epitaxial layer mayform a gate layer of the fin-based JFET device. In one embodiment, theregrown III-nitride epitaxial layer has a conductivity type opposite theconductivity type of the first, second, and third III-nitride epitaxiallayers.

Method 100 further includes forming a dielectric layer (120), formingvias through the dielectric layer (122), forming a source metal pad overthe dielectric layer and in the vias (124), and forming a drain layerelectrically coupled to the III-nitride substrate (126). The sourcecontact can be formed using a source metal that is deposited on thethird III-nitride layer before fin formation or on the fins after findefinition performed in relation to the formation of the recess regions.The gate contact can be a patterned structure that is formed on theregrown III-nitride epitaxial layer. The drain contact can be depositedon the opposing side of the substrate with respect to the source contactand the drain contact.

It should be appreciated that the specific steps illustrated in FIG. 1provide a particular method of fabricating a vertical fin-based JFETdevice with a regrown gate layer according to an embodiment of thepresent invention. Other sequences of steps may also be performedaccording to alternative embodiments. For example, alternativeembodiments of the present invention may perform the steps outlinedabove in a different order. Moreover, the individual steps illustratedin FIG. 1 may include multiple sub-steps that may be performed invarious sequences as appropriate to the individual step. Furthermore,additional steps may be added or removed depending on the particularapplication. One of ordinary skill in the art would recognize manyvariations, modifications, and alternatives.

FIGS. 2A through 2D are cross-sectional views showing intermediatestages of a method of fabricating a vertical fin-based JFET deviceaccording to an embodiment of the present invention. Referring onceagain to FIG. 1 and with reference to FIGS. 2A through 2D, the method offabricating a vertical fin-based JFET device is described in relation toa cross-section through an array of fin-based JFETs. Referring to FIG.2A, an n-type III-nitride substrate 200 is provided. The n-typeIII-nitride substrate 200 can be heavily doped with n-type dopants in adopant concentration in a range of about 5×10¹⁷ atoms/cm³ to about1×10¹⁹ atoms/cm³ and a resistivity of less than 0.020 ohm-cm. In oneembodiment, the resistivity of the n-type III-nitride substrate 200 maybe from about 0.001 ohm-cm to 0.018 ohm-cm, preferably less than 0.016ohm-cm, and more preferably, less than 0.012 ohm-cm.

In this embodiment, a first n-type semiconductor layer 201, which willserve as a drift layer, is epitaxially grown on n-type III-nitridesubstrate 200 at a temperature between 950 and 1200° C., preferablybetween 1000 and 1150° C., and more preferably about 1100° C. The firstn-type semiconductor layer 201 can have a thickness of about 12 μm and adopant concentration in a range of about 1×10¹⁶ atoms/cm³. In someembodiments, a graded doping region 202 having a thickness of about 0.3μm is disposed between the first n-type semiconductor layer 201 and thesecond n-type semiconductor layer 203 and has a dopant concentrationthat increases (e.g., linearly) from about 1×10¹⁶ atoms/cm³ to 1.3×10¹⁷atoms/cm³, i.e., from the first n-type semiconductor layer toward thesecond n-type semiconductor layer.

A second n-type semiconductor layer 203, which will serve as the channellayer, is epitaxially grown on graded doping region 202, or on firstn-type semiconductor layer 201 in embodiments in which graded dopingregion 202 is optional, at a temperature between 950 and 1200° C.,preferably between 1000 and 1150° C., and more preferably about 1100° C.As described more fully herein, the second n-type semiconductor layer203 will form a fin conduction layer and can be a uniformly doped regionwith n-type dopants of about 1.3×10¹⁷ atoms/cm³ and a thickness of about0.8 μm. A third III-nitride semiconductor layer 204, which may form thesource, is formed on second n-type semiconductor layer 203. The thirdIII-nitride semiconductor layer 204 may be a heavily doped n-type layerthat serves to improve the contact resistance between the second n-typesemiconductor layer 203 and the metal layer 205, which then serves asthe source contact.

Referring to FIG. 2B, a metal layer 205 is deposited on thirdIII-nitride semiconductor layer 204 and a patterned hard mask 206 isformed on metal layer 205. In an embodiment, the metal layer 205 mayinclude TiN and the patterned hard mask can be formed from a layer thatincludes silicon nitride e.g., Si₃N₄, with a thickness of about 400 nm.The Si₃N₄ layer can be formed by PECVD at about 300° C. In anembodiment, patterned hard mask 206 may be formed using RIE with F-basedchemistry. In an embodiment, metal layer 205 is omitted.

Referring to FIG. 2C, an etch process is performed using the patternedhard mask 206 as a mask to form a plurality of fins 203′, sources 204′,and source contacts 205′. In some embodiments, the fins 203′ each have awidth of about 0.2 μm, and a thickness in a range between about 0.7 μmand 0.8 μm, and are spaced apart from each other by a space of about 2μm, i.e., the fin pitch is about 2 μm. To have a uniform thickness forthe fins, good controllability of the depth of the etch process isutilized. In accordance with the present disclosure, an etch process mayinclude Cl-based chemistry using ME and is carried out to remove aportion of second n-type semiconductor layer 203 to form a recess region208. In an embodiment, the etch process may stop when about 0.1 μm ofgraded doping region 202 is removed. The graded doping region 202 isutilized in some embodiments to mitigate the electrical effects of theetch process variation or tolerance.

It is noted that the bottom portion of the fins may have a shapedifferent from the shape shown in FIG. 2C after the etch process.Embodiments of the present disclosure are described herein withreference to cross-section illustrations that are schematicillustrations of idealized embodiments (and intermediate structures) ofthe invention. The thickness of layers and regions in the drawings maybe exaggerated for clarity. Additionally, variations from the shapes ofthe illustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected. Thus, embodiments of theinvention should not be construed as limited to the particular shapes ofregions illustrated herein but are to include deviations in shapes thatresult, for example, from manufacturing. In the following drawings, thebottom portions of the fins are shown as having a 90 degrees angle withthe surface of the graded doping region, i.e., the fins are shown ashaving a cross-sectional rectangular shape. It is understood that thebottom portions of the fins may have rounded or curved features. Thus,the regions illustrated in the figures are schematic in nature and theirshapes are not intended to illustrate the actual shape of a region of adevice and are not intended to limit the scope of the invention.

In one embodiment, after forming the trench, a cleaning process iscarried using a tetramethylammonium hydroxide (TMAH) solution of about25% by weight, at a temperature of about 85° C., and for a duration ofabout 30 minutes. In another embodiment, prior to performing a cleaningusing the TMAH solution, a pre-cleaning such as piranha clean usingH₂SO₄:H₂O in a volume ratio 2:1 for 2 minutes may also be performed.

Referring to FIG. 2D, after the cleaning, a fourth semiconductor layer207 is epitaxially grown in recess region 208. In an embodiment, fourthsemiconductor layer 207 may include a p-type GaN layer that is grownnon-conformally in the trench at a temperature of about 950° C. up to athickness that is substantially planar to the bottom of source contacts205′. In one embodiment, the thickness of fourth semiconductor layer 207is about 1,000 nm. Accordingly, in some embodiments, the regrowth issubstantially planar with the bottom of the patterned growth mask, thatis, above sources 204′. The thickness of the regrowth can take inaccount the thickness of second n-type semiconductor layer 203, the etchinto the graded doping region 202, and the thickness of thirdIII-nitride semiconductor layer 204. The target deposition thickness onan unpatterned wafer is thinner due to the growth rate enhancement fromthe hardmask regions in the device area. The p-type GaN layer may bedoped with Mg with a dopant concentration of about 1×10′⁹ atoms/cm³. Thep-type GaN layer may be doped with Mg with a dopant concentration ofabout 1×10¹⁹ atoms/cm³. Thereafter, a thermal anneal (e.g., a rapidthermal annealing in N₂ at 850° C. for 5 minutes) is performed toactivate the Mg dopant atoms. The Mg atoms are then activated in thep-type GaN layer in an amount of greater than 10% by weight. Asillustrated in FIGS. 2C and 2D, sources 204′ are formed from the heavilydoped n-type layer present between fins 203′ and source contacts 205′ toimprove contact resistance between the second N-type semiconductor layerand the metal layer.

FIG. 3 is a plan view of a fin pattern layout illustrating a fin array300 having a plurality of semiconductor fins having fins ofpredetermined height according to an embodiment of the presentdisclosure. In this plan view, the gate metal is not shown. Additionaldescription related to fin arrays is provided in U.S. Patent ApplicationPublication No. 2021/0210624, the disclosure of which is herebyincorporated by reference in its entirety for all purposes.

Fins used in embodiments of the present invention can be bar-shaped finshaving a fin height smaller than 100 μm, e.g., 50 μm, 25 μm, or thelike. In other words, a fin can be formed by breaking up a long fin intomultiple small fin segments. For example, a fin of 1,000 μm height canbe divided into 40 fins, each having a ˜25 μm height. Referring to FIG.3, fin array 300 includes a plurality of fins arranged in a plurality ofrows (row 1, row 2, row m) and in a plurality of columns (column 1,column, 2, . . . , column n). The fins in each row are separated fromeach other by a pitch P. Each row is separated from each other by aspace S (i.e., the gap between each row). The total height of the array(AH) is now related to the individual fin height H, the number of rowsN, and the space S by AH=N*H+(N−1)*S. In one embodiment, the space S hasa size equal to the pitch P. In another embodiment, the space S can havea size greater than a single pitch P (e.g., 1.2×P, 1.5×P, or 2×P). It isunderstood that the number of rows and the number of columns can be anyinteger number. In one embodiment, the number of columns in differentrows may be different, for example, to enable “rounding” of the arrayfor improved junction-terminated edge designs. In the example shown inFIG. 3, six fins are used in each row (three rows and six columns areshown), but it is understood that the number of fins and the number ofrows and columns are arbitrarily chosen for describing the exampleembodiment and should not be limiting.

In one exemplary embodiment, the fin height H measured along the y-axisis about 25 μm, the fin width W measured along the x-axis is about 0.2μm, the fin thickness measured along the z-direction is about 0.8 μm,and the pitch P is in the range between 1.5 μm and 2.5 μm. In oneembodiment, a ratio between a fin width W and a pitch P between twoadjacent fins is in the range between about 0.08 and 0.15, preferably inthe range between 0.1 and 0.12. In one embodiment, a ratio between a finheight H and the pitch P between two adjacent fins is in the rangebetween 5 and 25, preferably between 10 and 20, and more preferablybetween 12 and 16. In one embodiment, the fin height H is about 25 μmand the fin width W is in the range between 0.15 μm and 0.7 μm.

In operation, the fins will form the channels of the FinFET and the gatemetal will be deposited between adjacent fins. As a result, the designillustrated in FIG. 3 can be referred to as a “gate-all-around” designin which the gate surrounds the fins.

FIGS. 4A and 4B show examples of a plan-view layout of an array of finswithout and with inactive fins, respectively, according to an embodimentof the present invention. In FIG. 4A, an active fin array 410 isillustrated. The boundary 412 of the active fin array 410 is alsoillustrated. The active fin array 410 includes a plurality of fins 405arranged in a two dimensional array. For purposes of clarity, only tworows of fins, each including six fins, are illustrated, but it will beappreciated that the array dimensions are not limited to this example.

As described above and more fully in relation to FIGS. 5A and 5B, theinventors have found that the local uniformity of the growth (e.g., theuniformity of the thickness of the regrowth between fins from gateregion to gate region) is impacted by edge effects present at theboundary 412 of the active fin array 410. Accordingly, embodiments ofthe present invention improve regrowth uniformity and enable thefabrication of an active fin array with uniform gate regrowth. Achievinguniform gate regrowth enables minimum variation in channel length (i.e.,the length of the channel extending along the z-direction aligned withthe thickness of the fins in the fin array across a large area). In someembodiments, the fin array can extend more than one millimeter in thex-direction and/or the y-direction, and use of the methods andstructures described herein can result in regrowth non-uniformity of <2%of the nominal regrowth thickness, i.e., a variation in regrowththickness of <15 nm for fins of nominal thickness of 0.75 μm.

In addition to regrowth thickness uniformity, improvements in fin widthuniformity are provided by embodiments of the present invention. At theboundary 412 of the active fin array 410, the amount of photoresistdeveloper outside the active fin array is different than the amount ofphotoresist developer inside the active fin array, resulting in agradient of developer across the active fin array 410. In conditions inwhich the developer concentration is lower inside the active fin arrayin comparison with outside the active fin array, the linewidth of thefin definition mask, e.g., the patterned hard mask or patterned metalmask, can vary. This will result, during the fin definition process, indifferences in the fin critical dimension (CD) near the edges of theactive fin array compared to the center of the active fin array.Moreover, the etch process can be impacted by edge effects. Duringetching of the gate trench, a large area outside the active fin array isetched in comparison to a smaller area inside the active fin array. As aresult, the etch loading will vary near the edges of the active finarray, resulting in variations in the etch rate and, as a result,variation in the depth of the gate trench across the active fin array.Variation in the depth of the gate trench can then result in variationin the uniformity of the thickness of the regrown material disposedbetween fins.

Referring to FIG. 4B, the addition of one or more inactive fin columns420 on a first side of active fin array 410 as well as one or moreinactive fin columns 421 on a second side of active fin array 410opposing the first side and one or more inactive fin rows 430 on a thirdside of active fin array 410 and one or more inactive fin rows 431 on afourth side of active fin array 410 opposing the third side result in anincrease in regrowth uniformity, active fin CD, and uniform gate trenchetch depth in the active fin array 410. The regrowth uniformity enabledby embodiments of the present invention mitigates a number of adverseconsequences that would otherwise result from regrowth non-uniformity.These adverse consequences can include: the gate metal layer havingdifferent thicknesses for different gates, which causes the metal gateresistivity to vary; unequal channel lengths that cause a highconcentration of the current on the short regrown gate area (e.g., a hotspot) that may exceed the maximum permissible temperature value andreduce the device reliability; uneven topography for self-alignedcontacts; and higher leakage current.

Referring to FIG. 4B, an array of fins with both an active fin array410, which will typically have many more active fins than illustrated,and inactive fins is illustrated. In FIG. 4B, the inactive fins, whichcan also be referred to as dummy fins, are arranged in multiple columnsto the left (inactive fin columns 420) and right (inactive fin columns421) of the active fin array 410 and in one row to the top (inactive finrow 430) and bottom (inactive fin row 431) of the active fin array 410.In FIG. 4B, three inactive fins make up inactive fin column 420, threeinactive fins make up inactive fin column 421, one row of inactive finsmake up inactive fin row 430, and one row of inactive fins make upinactive fin row 431, but the number of inactive fin columns andinactive fin rows can be greater than the number illustrated in FIG. 4B.Similarly, the number of rows and columns of active fins in the activefin array 410 can also be greater than illustrated. As described morefully in relation to FIG. 9, the inactive fins in the inactive fincolumns 420/421 and the inactive fin rows 430/431 do not include sourcecontacts and do not participate in the current flow occurring in theactive fin array 410 during operation. However, the inactive fins resultin improvements in regrowth uniformity that lead to improved deviceperformance of the FinFETs in the active fin array 410.

Although the inactive fins in the inactive fin columns 420/421 have thesame fin width and fin pitch as the active fins in the active fin array410, this is not required by the present invention and the fin width andthe fin pitch in the inactive fin columns 420/421 can differ from thatin the active fin array 410. As an example, the pitch of the inactivefins in the inactive fin columns 420/421 could not only be differentthan the pitch in the active fin array 410, but the pitch could varyacross the inactive fin columns 420/421. Additionally, the inactive finsin the inactive fin columns 420/421 can have different fin heights thanthe active fins in the active fin array 410. Moreover, the inactive finsin the inactive fin row 430/431, although they are illustrated as havingthe same fin width and fin pitch as the active fins in the active finarray 410, do not have to have the same fin width and the fin pitch asthe active fins in the active fin array 410. Additionally, the inactivefins in the inactive fin row 430/431 can be offset along the x-directionwith respect to the active fins in the active fin array 410, providing avariation on the embodiment illustrated in FIG. 4B, in which theinactive fins are aligned with the active fins. One of ordinary skill inthe art would recognize many variations, modifications, andalternatives.

Irregular edges (e.g., fitting the array to a circular arc of an edgetermination) may be accommodated by, for example, “stair-stepping” theactive fin array boundary with appropriate combinations of additionalrows of inactive fins and additional columns of inactive fins.

FIG. 5 shows a cross-section of an array of fins in an active fin arraycharacterized by regrowth non-uniformity according to an embodiment ofthe present invention. In FIG. 5, the cross-section is taken alongdirection A-A′ shown in FIG. 4A. As illustrated in FIG. 5, elementsdiscussed in relation to FIGS. 2A-2D are shown, including n-typeIII-nitride substrate 200, first n-type semiconductor layer 201, fins203′ formed from second N-type semiconductor layer 203 illustrated inFIG. 2A, and fourth semiconductor layer 207, i.e., the regrown p-typeGaN layer serving as the gate. Source contacts 205′ are illustrated. Anumber of non-uniformities in the fin array due to edge effects can bepresent in the cross-section illustrated in FIG. 5, including irregularor incomplete p-GaN gate growth, irregular p-GaN gate dopantincorporation, and variation in fin dimensions.

Referring to FIG. 5, the thickness of the fourth semiconductor layer207, also referred to as the regrown p-GaN gate, varies as a function oflateral dimension (i.e., along the x-direction) due to edge effects atthe edge of the fin array. The thickness varies from thickness t₁ atportions of the fin array adjacent the center of the fin array tothickness t₂ at the edge of the fin array. Although the decrease inthickness is illustrated as step 510, it will be appreciated that FIG. 5is merely a schematic diagram and the thickness variation can be presentin other morphologies. In some embodiments, as illustrated in FIG. 5,the regrowth thickness decreases near the edge of the fin array, forexample, resulting in a concave regrowth surface, with the thinnestportion of the regrowth positioned between adjacent fins. In otherembodiments, the regrowth thickness increases near the edge of the finarray, resulting in overgrowth to thicknesses higher than the finthickness. Although it is not illustrated in FIG. 5, variation in gatetrench depth can also be present.

In addition to regrowth thickness non-uniformity, the regrown materialmay also be characterized by variation in doping concentration. Becauseregrowth rates are different on different planes of the GaN hexagonalcrystal, for example, the m-planes and the c-planes, the dopantincorporation can vary depending on the growth plane.

Moreover, in addition to regrowth thickness, the fin width can vary as afunction of lateral dimension (i.e., along the x-direction). Asillustrated, in FIG. 1, the fin width, which, as discussed above, isdefined, in part, by the dimension of the mask used to etch the gatetrenches, varies from width W₁ adjacent the center of the fin array towidth W₂ at the edge of the fin array. Although a decrease in fin widthis illustrated in FIG. 5, it will be appreciated that the fin widthvariation can be present in other manners. In some embodiments, asillustrated in FIG. 5, the fin width decreases near the edge of the finarray, whereas, in other embodiments, the fin width increases near theedge of the fin array.

FIG. 6 shows a cross-section of a fin in an active fin arraycharacterized by regrowth non-uniformity according to an embodiment ofthe present invention. In FIG. 6, the cross-section is taken alongdirection B-B′ shown in FIG. 4A. FIG. 6 shares common elements with FIG.5 and the description provided in relation to FIG. 5 is applicable toFIG. 6 as appropriate. Although multiple non-uniformities can be presentin relation to the fin illustrated in FIG. 6, the discussion hereinfocuses on regrowth non-uniformity.

Referring to FIG. 6, the thickness of the fourth semiconductor layer207, also referred to as the regrown p-type GaN gate, varies as afunction of lateral dimension (i.e., along the x-direction) due to edgeeffects at the edge of the fin array. The thickness decreases fromthickness t₁ at portions of the fin adjacent the center of the fin arrayto thickness t₂ at the end of the fin. In FIG. 6, the decrease inthickness is illustrated as curve 610, but it will be appreciated thatFIG. 6 is merely a schematic diagram and the thickness variation can bepresent in other morphologies. In some embodiments, as illustrated inFIG. 6, the regrowth thickness decreases near the end of the fin, but inother embodiments, the regrowth thickness increases near the end of thefin, resulting in overgrowth to thicknesses higher than the finthickness. Although they are not illustrated in FIG. 6, variation ingate trench depth, variation in doping concentration, and variation infin width can also be present.

FIG. 7 shows a cross-section of an array of fins in an active fin arrayand inactive fin columns according to an embodiment of the presentinvention. In FIG. 7, the cross-section is taken along direction A-A′shown in FIG. 4A. As discussed in relation to FIG. 5, near the end ofthe array of fins, in this example, in the area of the inactive fincolumns 420, the thickness of the fourth semiconductor layer 207, alsoreferred to as the regrown p-GaN gate, varies as a function of lateraldimension (i.e., along the x-direction) due to edge effects at the edgeof the fin array. In addition to regrowth thickness non-uniformity, theother non-uniformities discussed above, including fin width variationand non-uniform dopant incorporation, may also be present. Asillustrated in FIG. 7, the regrowth non-uniformity is present in theinactive fin columns 420, but not in the active fin array 410, which ischaracterized by uniform regrowth. Thus, in this embodiment, theregrowth non-uniformity, as well as the other non-uniformities discussedherein, is limited to the columns of inactive fins, which do notcontribute to current flow though the FET device.

It should be noted that the source contacts 520 are only formed on finsin the active fin array 410 and not on the fins in the inactive fincolumns 420 since the inactive fins do not contribute to current flowthrough the FET device. It should be noted that the source contacts 205′are shown in FIGS. 5 and 7 merely to illustrate the location of the finsurface, since the source contacts can be positioned behind the plane ofthe cross-section, in a manner similar to the positioning of the fins insome embodiments.

FIG. 8 shows a cross-section of a fin in an active fin array and aninactive fin row according to an embodiment of the present invention. InFIG. 8, the cross-section is taken along direction B-B′ shown in FIG.4A. FIG. 8 share common elements with FIG. 7 and the descriptionprovided in relation to FIG. 7 is applicable to FIG. 8 as appropriate.Although multiple non-uniformities can be present in relation to theinactive fin illustrated in FIG. 8, the discussion herein focuses onregrowth non-uniformity.

Referring to FIG. 8, the thickness of the fourth semiconductor layer207, also referred to as the regrown p-GaN gate, varies as a function oflateral dimension (i.e., along the y-direction) due to edge effects atthe edge of the fin array. As discussed in relation to FIG. 7, near theend of the array of fins, in this example, in the area of the inactivefin row 430, the thickness of the fourth semiconductor layer 207, alsoreferred to as the regrown p-GaN gate, varies as a function of lateraldimension (i.e., along the y-direction) due to edge effects at the edgeof the fin array. In addition to regrowth thickness non-uniformity, theother non-uniformities discussed above, including fin width variationand non-uniform dopant incorporation, may also be present. Asillustrated in FIG. 8, the regrowth non-uniformity is present in theinactive fin row 430, but not in the active fin array 410, which ischaracterized by uniform regrowth. Thus, in this embodiment, theregrowth non-uniformity, as well as the other non-uniformities discussedherein, is limited to the columns of inactive fins, which do notcontribute to current flow through the FET device.

FIG. 9 shows a cross-section of an array of fins in an active fin arrayand inactive fin columns with a source pad metal according to anembodiment of the present invention. In FIG. 9, the cross-section istaken along direction A-A′ shown in FIG. 4A. As illustrated in FIG. 9,electrical connection between the source pad metal 910 and sourcecontacts 205′ is provided through vias 920 passing through dielectriclayer 930. No vias are present between the source pad metal 910 and theinactive fins in the inactive fin columns 420/421. In this embodiment,the source contact metal forming source contacts 205′ is not present onthe inactive fins in a manner similar to that shown in FIGS. 7 and 8. Inother embodiments, the source contact metal is present on the inactivefins but the lack of vias and the presence of the dielectric layerprevents the inactive fins from being electrically active. Although theinactive fins do not contribute to current flow in the FET device, theyprovide a region of predetermined dimensions between the active finarray and the area surrounding the active fin array, thereby resultingin uniform regrowth in the active fin array.

Embodiments of the present invention are applicable to arrays offin-based vertical FETs in which the current runs vertically along thefin and the arrays of fins are enclosed by a gate-all-around structureso that all fins have a common gate. The gate-channel interface can belocated on the vertical sidewall of the vertical fin. The FETs may beJFETs with regrown gates, implanted gates, or diffused gates, or theymay be MOSFETs, including accumulation-mode MOSFETs. The fin-basedvertical FETs can be fabricated using III-nitride semiconductors. In anembodiment, the fin-based vertical FETs are fabricated using GaN. In anembodiment, the number of inactive fin columns is between 1 and 10, andthe number of inactive fin rows is between 1 and 5. In an embodiment,the inactive fin rows use fins of shorter height (as discussed inrelation to FIG. 4B) than the active fins in the active fin array. In anembodiment, the inactive fin row height is comparable to the width ofthe region encompassed by the inactive fin columns. Additionaldescription related to implanted gates and diffused gates is provided incommonly assigned U.S. patent application Ser. No. 17/667,432, filed onFeb. 8, 2022, the disclosure of which is hereby incorporated byreference in its entirety for all purposes.

FIG. 10 is a cross-section view of an alternative vertical, fin-basedgate-all-around JFET device using implanted or diffused gates accordingto an embodiment of the present invention. In the alternative embodimentillustrated in FIG. 10, the regrown gate structure illustrated in FIG.2D has been replaced with implanted or diffused gates. Although only aportion of the JFET device is illustrated in FIG. 10, it will beappreciated that the illustrated structure can be implemented as aportion of an active fin array in conjunction with inactive fin columnsand one or more inactive fin rows as described more fully herein. Theuse of the inactive fin columns and one or more inactive fin rowsenables the formation of uniform fins as described herein.

In FIG. 10, a source metal contact structure 1012 is formed on an upperportion of a second III-nitride layer 1006, which is coupled to a firstIII-nitride layer 1004. Thus, source metal contact structure 1012 isformed on the fins. Source metal contact structure 1012 is electricallyisolated from the semiconductor gate region 1011. In FIG. 10,semiconductor gate region 1011 extends along the sidewall of the fin anda physical separation S between semiconductor gate region 1011 andsource metal contact structure 1012 can be utilized to provideelectrical isolation. In some embodiments, the source metal contactstructure 1012 forms a self-aligned contact to the upper portion ofsecond III-nitride layer 1006. In some embodiments, the source metalcontact structure 1012 includes a hard mask metal layer. The sourcemetal contact structure 1012 may include titanium, aluminum, titaniumnitride, combinations thereof, or the like.

Gate metal contact structure 1014 is formed on the upper portion ofsemiconductor gate region 1011. In some embodiments, the gate metalcontact structure 1014 can include a metallic structure. For example,the metallic structure may include nickel, palladium, silver, gold,combinations thereof, and the like. The metallic structure can make anohmic contact with the semiconductor gate region 1011, which can be ap-type semiconductor gate region. An edge termination 1016 is formed onthe p-type layer used as the semiconductor gate region 1011 to enablehigh-voltage operation of the device. The p-type layer may also beconnected to the source in some embodiments. A drain metal contactstructure 1018 is formed on a second side, i.e., the backside, ofIII-nitride substrate 1002. The drain metal contact structure 1018 canform an ohmic contact to the III-nitride substrate 1002. In someembodiments, the drain metal contact structure 1018 can includetitanium, aluminum, or combinations thereof. In some embodiments, thedrain metal contact structure 1018 can further include a solderablemetal structure such as silver, lead, tin, combinations thereof, or thelike.

The semiconductor gate region 1011 can be a diffused gate structure inwhich a diffusion source is utilized in a process in which diffusiondopants are incorporated into second III-nitride layer 1006 and firstIII-nitride layer 1004. As an example, a layer of a diffusion dopantmaterial may be applied to the surfaces of the fins and firstIII-nitride layer 1004. In some embodiments, the layer of diffusiondopant material may include either a metal layer formed with a p-typedopant (e.g., Mg, Zn, combinations thereof, and the like) or a metallicoxide layer formed with a p-type dopant (e.g., MgO, ZnO, combinationsthereof, and the like), in contact with the exposed III-nitride surfacesof the fins. In some embodiments, the thickness of the metal or metallicoxide layer is 50-100 nm. In some embodiments, the layer of diffusiondopant material may further include a second layer of dielectricmaterial (e.g., SiO₂, Si₃N₄ or the like) disposed on the metal ormetallic oxide layer.

A thermal treatment can be used to diffuse the p-type dopant into theexposed surfaces of the first III-nitride layer 1004 and the secondIII-nitride layer 1006. The resulting channel can have a width of thefin width minus twice the diffusion depth. In some embodiments, thethermal treatment may be performed in a furnace at temperatures from900° C. to 1100° C. In some embodiments, the thermal treatment may beperformed in a rapid thermal annealer at temperatures from 1000° C. to1450° C. In some embodiments the thermal treatment may be performed at ahigh ambient pressure (e.g., at 1 GPa in a N₂ ambient), with or withoutthe protective layer. In some embodiments, the heating may be a resultof a series of rapid pulses (e.g. microwave). After diffusion, thediffusion dopant material may be removed, for example, by using a wetetch.

In other embodiments, rather than diffusion, ion implantation isutilized to form implanted gate regions. Accordingly, the discussionprovided in relation to FIG. 10 with respect to diffusion doping can beapplied in the context of ion implantation and annealing to formimplanted gate regions. One of ordinary skill in the art would recognizemany variations, modifications, and alternatives.

FIG. 11 is a cross-section view of an alternative vertical, fin-basedgate-all-around MOSFET device according to an embodiment of the presentinvention. The alternative embodiment illustrated in FIG. 11 illustratestwo active fins that can be implemented as a portion of an active finarray in conjunction with inactive fin columns and one or more inactivefin rows as described more fully herein. The use of the inactive fincolumns and one or more inactive fin rows enables the formation ofuniform fins as described herein. Referring to FIG. 11, substrate 1102,for example, an n-type GaN substrate, supports drift layer 1104 andgraded layer 1106. Fins 1120 are formed in contact with graded layer1106. Source contact 1112 is electrically connected to fin 1120 and achannel region is operated in conjunction with gate 1110, which iselectrically isolated by dielectric 1108. During operation of thisaccumulation mode MOSFET, in response to gate bias, vertical currentflow from source contact 1112 to drain contact 1114 passes through fins1120.

Thus, in a manner similar to that discussed with respect to the JFETdevice discussed in relation to FIG. 10, the MOSFET device illustratedin FIG. 11 can use the inactive fin columns and one or more inactive finrows to form uniform fins as described herein.

While various embodiments of the invention have been described above, itshould be understood that they have been presented by way of exampleonly, and not by way of limitation. Likewise, the various diagrams maydepict an example architectural or other configuration for thedisclosure, which is done to aid in understanding the features andfunctionality that can be included in the disclosure. The disclosure isnot restricted to the illustrated example architectures orconfigurations, but can be implemented using a variety of alternativearchitectures and configurations. Additionally, although the disclosureis described above in terms of various exemplary embodiments andimplementations, it should be understood that the various features andfunctionality described in one or more of the individual embodiments arenot limited in their applicability to the particular embodiment withwhich they are described. They instead can be applied alone or in somecombination, to one or more of the other embodiments of the disclosure,whether or not such embodiments are described, and whether or not suchfeatures are presented as being a part of a described embodiment. Thus,the breadth and scope of the present disclosure should not be limited byany of the above-described exemplary embodiments.

It will be appreciated that, for clarity purposes, the above descriptionhas described embodiments of the invention with reference to differentfunctional units and processors. However, it will be apparent that anysuitable distribution of functionality between different functionalunits, processors or domains may be used without detracting from theinvention. For example, functionality illustrated to be performed byseparate processors or controllers may be performed by the sameprocessor or controller. Hence, references to specific functional unitsare only to be seen as references to suitable means for providing thedescribed functionality, rather than indicative of a strict logical orphysical structure or organization.

Terms and phrases used in this document, and variations thereof, unlessotherwise expressly stated, should be construed as open ended as opposedto limiting. As examples of the foregoing: the term “including” shouldbe read as meaning “including, without limitation” or the like; the term“example” is used to provide exemplary instances of the item indiscussion, not an exhaustive or limiting list thereof; and adjectivessuch as “conventional,” “traditional,” “normal,” “standard,” “known”,and terms of similar meaning, should not be construed as limiting theitem described to a given time period, or to an item available as of agiven time. But instead these terms should be read to encompassconventional, traditional, normal, or standard technologies that may beavailable, known now, or at any time in the future. Likewise, a group ofitems linked with the conjunction “and” should not be read as requiringthat each and every one of those items be present in the grouping, butrather should be read as “and/or” unless expressly stated otherwise.Similarly, a group of items linked with the conjunction “or” should notbe read as requiring mutual exclusivity among that group, but rathershould also be read as “and/or” unless expressly stated otherwise.Furthermore, although items, elements or components of the disclosuremay be described or claimed in the singular, the plural is contemplatedto be within the scope thereof unless limitation to the singular isexplicitly stated. The presence of broadening words and phrases such as“one or more,” “at least,” “but not limited to”, or other like phrasesin some instances shall not be read to mean that the narrower case isintended or required in instances where such broadening phrases may beabsent.

It is also understood that the examples and embodiments described hereinare for illustrative purposes only and that various modifications orchanges in light thereof will be suggested to persons skilled in the artand are to be included within the spirit and purview of this applicationand scope of the appended claims.

What is claimed is:
 1. A vertical, fin-based field effect transistor (FinFET) device comprising: an array of individual FinFET cells, the array comprising a plurality of rows and columns of separated fins, wherein each of the separated fins is in electrical communication with a source contact; one or more rows of first inactive fins disposed on a first set of sides of the array of individual FinFET cells; one or more columns of second inactive fins disposed on a second set of sides of the array of individual FinFET cells; and a gate region surrounding the individual FinFET cells of the array of individual FinFET cells, the first inactive fins, and the second inactive fins.
 2. The FinFET device of claim 1 wherein a height of the first inactive fins is less than a height of the separated fins in the array of individual FinFET cells.
 3. The FinFET device of claim 1 wherein the first inactive fins and the second inactive fins do not have associated source contacts.
 4. The FinFET device of claim 1 wherein the individual FinFET cells comprise regrown gate FinFETs.
 5. The FinFET device of claim 1 wherein the individual FinFET cells comprise diffused gate FinFETs.
 6. The FinFET device of claim 1 wherein the individual FinFET cells comprise implanted gate FinFETs.
 7. The FinFET device of claim 1 wherein the individual FinFET cells comprise MOSFETs.
 8. The FinFET device of claim 1 wherein: the FinFET device includes a plurality of source contacts and a plurality of channels; the gate region comprises a common gate; and the individual FinFET cells have a common drain.
 9. The FinFET device of claim 1 wherein the one or more rows of first inactive fins comprises between one row and ten rows per side.
 10. The FinFET device of claim 9 wherein the one or more rows of first inactive fins comprises one row per side.
 11. The FinFET device of claim 1 wherein the one or more columns of second inactive fins comprise between one and ten columns per side.
 12. The FinFET device of claim 11 wherein the one or more columns of second inactive fins comprise five columns per side.
 13. A method of fabricating a vertical, fin-based field effect transistor (FinFET) device, the method comprising: providing a III-nitride substrate including a plurality of epitaxial layers; forming a metal layer coupled to one of the plurality of epitaxial layers; patterning the metal layer to form source contacts; forming a recess region in one or more of the plurality of epitaxial layers to define an active fin array, inactive fin columns, and one or more inactive fin rows, wherein each of the source contacts is in electrical communication with an active fin in the active fin array; regrowing a gate layer in the recess region; forming a dielectric layer over the source contacts; forming vias through the dielectric layer; forming a source pad metal over the dielectric layer and in the vias, wherein the source pad metal is in electrical communication with the source contacts; and forming a drain layer electrically coupled to the III-nitride substrate.
 14. The method of claim 13 wherein inactive fins in the inactive fin columns and the one or more inactive fin rows do not have associated source contacts.
 15. The method of claim 13 wherein the FinFET device includes individual regrown gate FinFET cells.
 16. The method of claim 13 wherein the FinFET device includes individual diffused gate FinFET cells.
 17. The method of claim 13 wherein the FinFET device includes individual implanted gate FinFET cells.
 18. The method of claim 13 wherein the FinFET device includes individual MOSFETs.
 19. The method of claim 13 wherein: the FinFET device includes a plurality of source contacts and a plurality of channels; the gate layer comprises a common gate; and the FinFET device has a common drain.
 20. The method of claim 13 wherein: the one or more inactive fin rows include one or more rows of first inactive fins disposed on a first set of sides of the active fin array; and the inactive fin columns include a plurality of columns of second inactive fins disposed on a second set of sides of the active fin array. 